Image Image Image Image Image Image Image Image Image Image
Scroll to top


40 Inventive Principles in Microelectronics

40 Inventive Principles in Microelectronics

| On 10, Aug 2002

40 Inventive Principles in Microelectronics

By: Gennady Retseptor
© 2002. Gennady Retseptor. AVX Israel Ltd. 972-2-5720128. All rights reserved.

Both Microelectronics and TRIZ emerged independently around 50 years ago in Western countries and the former USSR.

Microelectronics has been already recognized as one of the tremendous achievements of XX century. TRIZ has started its proliferation in Western countries only in the last decade.

For people working in Microelectronics it may be interesting to know how technical solutions in their scope are looking from the point of view of TRIZ. This article is the author’s endeavor to make classification and summarize examples of TRIZ inventive principles in Microelectronics.

Editor’s note: There is some debate about whether one becomes more creative by reading examples of creative problem solving in fields other than one’s own, or if, for many people, examples in one’s own field are needed to get started understanding how the 40 principles work. The editor’s experience as a TRIZ teacher has been that most people need a mixture of examples from their own field and from others, so we have been very glad to publish lists of examples from many fields. (See References).

Principle 1. Segmentation/Fragmentation/Division

  1. Divide an object into independent parts.
    • Individual dies on Si (Silicon) wafer.
    • Two-stage diffusion process.
    • Beam splitting.
  2. Make an object easy to disassemble.
    • Integrated Circuits (IC) and passive components assembly on Multi-Chip Module (MCM).
    • Multi-chip modules assembly on ‘daughter’ board.
    • ‘Daughter’ boards assembly on ‘mother’ board.
  3. Increase the degree of fragmentation or segmentation.
    • Increase in number of gates per microprocessor chip (1.35 times per year).
    • Increase in number of bits per memory chip (1.5 times per year).
    • Increase in number of inputs/outputs (I/O) per chip and pins per package.
    • Sea of Lands (SOL) – ultra-high density packaging.
  4. Transition to micro-level.
    • Spray development and spray etching.
    • Sub-layers with different inherent stress at Microelectronic Mechanical Systems (MEMS).
    • Decrease of feature size (to 0.05 microns and less).
    • Molecular Beam Epitaxy (MBE).
    • Atomic Layer Deposition (ALD).
    • Nanometry.

Principle 2. Taking out/Separation/Removal/Extraction/Segregation

  1. Separate an interfering part or property from an object, or single out the only necessary part (or property) of an object.
    • Clean rooms.
    • Isolation of Copper areas at wafer fab.
    • Separation of wafers from people.
    • Cluster tooling.
    • Single wafer processing.
    • Impurities segregation at Si crystal growth (CZ process).
    • LOCOS isolation.
    • Barrier for Copper diffusion prevention.
    • Ion separation at ion implantation.
    • Etch stop layer.
    • Polarized light microscopy.
    • Die separation by grooves at Chip Scale Packaging (CSP).
    • Electrical and visual screening.
    • Burn-in.

Principle 3. Local quality

  1. Change an object’s structure from uniform to non-uniform, change an external environment (or external influence) from uniform to non-uniform.
    • Temperature gradient at CZ process, epitaxy, oxidation, diffusion.
    • Pressure gradient at Chemical Vapor Deposition (CVD).
    • Selectivity and anisotropy at wet and dry etching.
    • Impurities concentration gradient at diffusion with diverse doping profiles: exponent, power-law, step, grade.
    • Depletion layer.
    • Field Effect Transistor (FET) with arbitrary charge distribution.
  2. Make each part of an object function in conditions most suitable for its operation.
    • Single wafer processing: CVD, Physical Vapor Deposition (PVD), dry etching, etc.
  1. Make each part of an object fulfill a different and useful function.
    • Buried layer with opposite impurity type.
    • P-n-p pocket in n-p-n substrate at CMOS IC.

Principle 4. Asymmetry/Symmetry change

  1. Change the shape of an object from symmetrical to asymmetrical.
    • SEMI standard for Si wafers crystallographic orientation marking: <111>, <110>, <100>.
    • P-n junction asymmetry.
  2. Change the shape or properties of an object to suit external asymmetries.
    • Anisotropic plasma etching.
  3. If an object is asymmetrical, increase its degree of asymmetry.
    • Increasing features aspect ratio.

Principle 5. Merging/Combining/Composition/Integration/Agglomeration

  1. Bring closer together (or merge) identical or similar objects; assemble identical or similar parts to perform parallel operations.
    • Subtracting images from neighboring dies for visual defects detection.
    • Integrated circuit.
    • Multi-chip module.
    • Giga-scale Integration (GSI).
    • Giga-scale System on Chip (GSOC).
  2. Make operations contiguous or parallel; bring them together in time.
    • Multi-beam electron writing.
    • Wafer level clean rooms operations.
    • Wafer level SMD termination [6] .
    • Wafer level burn-in.
    • Wafer Level Packaging (WLP).
  3. Agglomerate objects to Bi- and Poly- system.
    • Bi-layers: Ti/TiN, Ta/TaN.
    • Chemical Mechanical Polishing (CMP).
    • Electrochemical Mechanical Deposition (ECMD).
    • Mechanical, electrical, magnet, plasma, etc. fields agglomeration.

Principle 6. Universality/Multi-functionality

  1. Make a part or object perform multiple functions; eliminate the need for other parts.
    • Multi-task dispensing system.
    • Multiple targets in sputtering machine.
    • Electron beam direct writing. No need for mask.
    • Plasma CF4 with Oxygen for both photoresist strip and surface cleaning in one process.
    • IC package substrate multi-function: multi-layer connection, heat dissipation, escaping I/O traces, controlled impedance, ground return.
    • Components packaging (tape and reel, bulk feed cassette, etc.) multi-function: components protection, transportation, and presentation to pick-and-place machine.
  2. Use standardized features.
    • International standards in Semiconductors and Microelectronics.
    • Visual workmanship standards.
    • Measurement, inspection and test equipment calibration.
    • Specifications for incoming, in-process and final quality inspection.
    • Specifications for functional, mechanical and environmental testing.

Principle 7. Nesting/”Nested doll”/Recess/Embedding

  1. Place one object inside another; place each object, in turn, inside the other.
    • Clean rooms and clean areas multi-step nesting.
    • P-n-p pocket in n-p-n substrate for CMOS IC.
    • Buried layer.
    • Inverse conductivity type area made by diffusion or ion implantation.
    • Multi-layer termination structure.
    • Electrical tolerances nesting.
    • Embedded air-gap region within SOL.
    • Recessed contact pad at D-BGA packaging.
    • Embedding of integrated passives into Low Temperature Co-fired Ceramic (LTCC) substrate at CSP.
    • Packaging hierarchy : chip – module – card – board – system.
    • Micro-packaging and meso-packaging integration at MEMS: die – device – system.
  1. Make one part pass (dynamically) through a cavity in the other.
    • MEMS micro-machines.

Principle 8. Counterweight/Anti-weight/Weight compensation/Levitation

  1. To compensate for the weight of an object, merge it with other objects that provide lift.
    • Levitation of wafer by air or Nitrogen cushion.
    • Transportation of ultra-thin wafer by floating.
  2. To compensate for the weight of an object, make it interact with the environment (e.g. use aerodynamic, hydrodynamic, buoyancy and other forces).
    • Capillary effects for cleaning and chemical treatment in trenches and vias.
    • Capillary action for solder drawing from tip to PCB pad.

Principle 9. Preliminary anti-action/Prior counteraction

  1. If it will be necessary to do an action with both harmful and useful effects, this action should be replaced with anti-actions to control harmful effects.
    • Si3N4 masking for LOCOS.
    • LOCOS masking for ion implantation.
    • Silicon oxide and poly-silicon masking for diffusion.
    • Resist masking for lithography.
    • Buffered oxide etchant.
    • Pre-cleaning before epitaxy, oxidation, diffusion, metallization, etc.
    • Infra-red wafer surface drying before photoresist coating.
    • Priming before polyimide or epoxy dispensing.
    • PCB masking by tape.

Principle 10. Preliminary action/ Prior action/Do it advance

  1. Perform, before it is needed, the required change of an object (either fully or partially).
    • Substrate cleaning.
    • Sputter targe